smp question

smp question

am 29.11.2004 18:04:30 von mlopezb

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Hello,
Sorry if this is a to silly question... :-X

I have a SMP capable server, but with only one cpu installed.
Should I enable SMP support on the kernel? I'm trying to reach the best
performance.
The cpu is Intel Xeon, this option is not in the cpu list in the kernel
config. Should I chose P4 or P3? it is the same?

BR,
Mat=EDas.

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Re: smp question

am 30.11.2004 00:56:45 von cummings

Mat=EDas L=F3pez Bergero wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>=20
> Hello,
> Sorry if this is a to silly question... :-X
>=20
> I have a SMP capable server, but with only one cpu installed.
> Should I enable SMP support on the kernel? I'm trying to reach the be=
st
> performance.
> The cpu is Intel Xeon, this option is not in the cpu list in the kern=
el
> config. Should I chose P4 or P3? it is the same?

IIRC, Xeon processors have dual internal cores (or at least dual=20
instruction decode paths), and act like dual processors, and benefit=20
from the SMP kernels. Also, IIRC, there were both P3 and P4 Xeons made=
.
So, you have to know which version you have.

What does "cat /proc/cpuinfo" tell you?

--=20
Kevin J. Cummings
kjchome@rcn.com
cummings@kjchome.homeip.net
cummings@kjc386.framingham.ma.us
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Re: smp question

am 30.11.2004 14:25:28 von mlopezb

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Kevin J. Cummings wrote:
| Mat=EDas L=F3pez Bergero wrote:
|> I have a SMP capable server, but with only one cpu installed.
|> Should I enable SMP support on the kernel? I'm trying to reach the b=
est
|> performance.
|> The cpu is Intel Xeon, this option is not in the cpu list in the ker=
nel
|> config. Should I chose P4 or P3? it is the same?
|
| IIRC, Xeon processors have dual internal cores (or at least dual
| instruction decode paths), and act like dual processors, and benefit
| from the SMP kernels. Also, IIRC, there were both P3 and P4 Xeons ma=
de.
| So, you have to know which version you have.
|
| What does "cat /proc/cpuinfo" tell you?
|

I'm seeing two processors, I had notes this before, but I was in doubt
if that output was produced by the SMP kernel, or the Xeon cpu, now
according to what you are telling me, it's a feature of the Xeon cpu ri=
ght?

Here is my cpuinfo:

sh-2.05b# cat /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu family : 15
model : 2
model name : Intel(R) Xeon(TM) CPU 2.80GHz
stepping : 9
cpu MHz : 2800.195
cache size : 512 KB
physical id : 0
siblings : 2
runqueue : 0
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 2
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2
ss ht tm
bogomips : 5583.66

processor : 1
vendor_id : GenuineIntel
cpu family : 15
model : 2
model name : Intel(R) Xeon(TM) CPU 2.80GHz
stepping : 9
cpu MHz : 2800.195
cache size : 512 KB
physical id : 0
siblings : 2
runqueue : 0
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 2
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2
ss ht tm
bogomips : 5596.77

sh-2.05b#

Thanks for ur help Kevin!

Best Regards,
Mat=EDas.
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Re: smp question

am 30.11.2004 17:56:21 von cummings

Mat=EDas L=F3pez Bergero wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>=20
> Kevin J. Cummings wrote:
> | Mat=EDas L=F3pez Bergero wrote:
> |> I have a SMP capable server, but with only one cpu installed.
> |> Should I enable SMP support on the kernel? I'm trying to reach the=
best
> |> performance.
> |> The cpu is Intel Xeon, this option is not in the cpu list in the k=
ernel
> |> config. Should I chose P4 or P3? it is the same?
> |
> | IIRC, Xeon processors have dual internal cores (or at least dual
> | instruction decode paths), and act like dual processors, and benefi=
t
> | from the SMP kernels. Also, IIRC, there were both P3 and P4 Xeons =
made.
> | So, you have to know which version you have.
> |
> | What does "cat /proc/cpuinfo" tell you?
> |
>=20
> I'm seeing two processors, I had notes this before, but I was in doub=
t
> if that output was produced by the SMP kernel, or the Xeon cpu, now
> according to what you are telling me, it's a feature of the Xeon cpu =
right?

If I remember Correctly, yes, its a feature of the XEON CPU. (I have=20
athlons here at home!)

> Here is my cpuinfo:
>=20
> sh-2.05b# cat /proc/cpuinfo
> processor : 0
> vendor_id : GenuineIntel
> cpu family : 15
> model : 2
> model name : Intel(R) Xeon(TM) CPU 2.80GHz

This looks like a P4 Xeon: 2.80GHz speed

> stepping : 9
> cpu MHz : 2800.195
> cache size : 512 KB
> physical id : 0
> siblings : 2

Yeup, looks like 2 instruction pipelines.

> runqueue : 0
> fdiv_bug : no
> hlt_bug : no
> f00f_bug : no
> coma_bug : no
> fpu : yes
> fpu_exception : yes
> cpuid level : 2
> wp : yes
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pg=
e
> mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2
> ss ht tm
> bogomips : 5583.66

And the second "processor":

> processor : 1
> vendor_id : GenuineIntel
> cpu family : 15
> model : 2
> model name : Intel(R) Xeon(TM) CPU 2.80GHz
> stepping : 9
> cpu MHz : 2800.195
> cache size : 512 KB
> physical id : 0
> siblings : 2
> runqueue : 0
> fdiv_bug : no
> hlt_bug : no
> f00f_bug : no
> coma_bug : no
> fpu : yes
> fpu_exception : yes
> cpuid level : 2
> wp : yes
> flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pg=
e
> mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2
> ss ht tm
> bogomips : 5596.77
>=20
> sh-2.05b#
>=20
> Thanks for ur help Kevin!

NP

--=20
Kevin J. Cummings
kjchome@rcn.com
cummings@kjchome.homeip.net
cummings@kjc386.framingham.ma.us
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