ANNOUNCE: Verilog-GetInfo-1.0.1.pm

ANNOUNCE:

Verilog-GetInfo-1.0.1.pm is being released in the directory
http://backpan.perl.org/authors/id/R/RO/ROHITM/Verilog-GetIn fo-1.0.1.pm


DESCRIPTION:

Verilog::Getinfo.pm is a complete verilog HDL language parser.

$handle = Verilog::GetInfo->new(\@command_line)';

Above command will return a handle to the new verilog design database.
@command_line is the verilog command line options understood by
GetInfo.
Most of the standard (IEEE 1364) command line options are supported.

Some of the options which are supported are:
-v, -y, + ( plusargs ), +define+, -l etc.

GetInfo understands most of the in-the-file options of Verilog HDL
language:
`ifdef...`else...`endif
`include "filename.v"
`define macro value
`define macro

Some of the functions which return information about the design are:

Get_Inputs( module_name ) - Returns list of input ports of the module.
It will return an array, with all the inputs along with their bus

widths.

Get_Outputs( module_name ) - Returns list of output ports of the
module.
An array with all the output ports listed along with their bus
widths.

Get_Ports( module_name ) - Returns list of ports of a module.

Get_Regs( module_name ) - Returns list of registers defined in a
module.

Get_Wires( module_name) - Returns list of wires defined in a module.

Get_Inouts( module_name) - Returns list of inout ports in a module.

Get_Toplevel() - Returns list of module names, which are not
instantiated
inside any other modules.

Hierarchy( module_name ) - The module_name can be any module in the
design.
Returns a reference to a hash containing the hierarchy
information of the
module. It will report all the sub-modules below the module
provided as the
input to the function.

Print_Hierarchy( module_name ) - This function calls the function
Hierarchy(),
and prints the hierarchy in the nice human readable form.

Get_Define() - If an input is given to this function it will check,
whether
it is defined. If it is defined, it will check whether its a
macro definition
and return the value of the macro.
If no input is given, it will return all the defines that have
been defined
in the design, with their values.


Get_Files() - This function returns all the design files read into the
database.

Get_Module_Count() - This function returns the total number of modules
in the design.

Get_Modules() - This functions lists all the modules in the design.

Get_Full_Design() - This function returns a full flat netlist in an
array. Note: The array will be huge.

Get_Module_Contents() - This function returns the contents ( without
comments )
of a module provided as an input to this function.

Message(), Warning(), Echo(), Error() - Display functions. Will display
lot
of information when parsing the design files.

BUGS:
No known bugs. Report all bugs to the author.

AUTHOR:
Rohit Mishra ( rohit[at]rohitmishra.com )